Development of a UVM-Based Verification IP for DO-254 Compliant ARINC429 HDL Modules

Abstract

ARINC429 is a widely adopted data transfer standard in avionics, ensuring reliable communication between critical onboard systems. As aircraft increasingly rely on complex electronics, compliance with safety standards such as DO-254 becomes essential for certifying airborne hardware. The verification of ARINC429 IP cores is crucial to meet these stringent safety requirements. Traditionally, ARINC429 IP cores in the literature have been verified using basic testbenches, which pose challenges in terms of flexibility, time, and cost. This paper introduces a UVM-based verification IP for DO-254 compliant ARINC429 HDL modules, addressing the limitations of conventional verification methods by enhancing test coverage and reducing development time. To the best of our knowledge, this is the first study in the literature that uses a VIP to verify an ARINC429 IP core for multiple test scenarios. The VIP offers a reusable, scalable, and efficient verification framework, serving as a robust alternative to traditional loopback-based approaches. It enables thorough validation of ARINC429 IP cores in complex avionics systems. The SIEMENS QuestaSim 10.7a simulator tool is used to extensively test an ASELSAN developed DO-254 compliant ARINC429 IP with the proposed VIP. The results indicate a branch coverage of 91.74%, a statement coverage of 98.34%, and an FEC expression coverage of 96.76%, with an overall average of 95.61% © 2025 Elsevier B.V., All rights reserved.