BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register Allocation

dc.contributor.authorTerci, Gizem Sungu
dc.contributor.authorAbdulhalik, Enes
dc.contributor.authorBayrakçı, Alp Arslan
dc.contributor.authorBoz, Betul
dc.date.accessioned2025-10-29T11:15:59Z
dc.date.issued2024
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümü
dc.description.abstractRegister allocation is important in compiler design to enhance the execution time of programs, as CPU registers operate significantly faster than memory locations. The challenge of optimally assigning program variables to a limited number of CPU registers requires innovative solutions within constrained timeframes, particularly when traditional methods are not applicable due to computational infeasibility on current CPU architectures. This study introduces BitVertex Evolutionary Algorithm (BitEA), a novel approach grounded in bitwise operations and bit-based solutions, designed to accelerate computational performance in register allocation. Our experimental results show that BitEA outperforms the existing methods by a factor of up to 60 across all tested scenarios in the DIMACS benchmarks. Furthermore, in terms of solution quality, BitEA achieves lower chromatic numbers on 9 DIMACS benchmarks compared to its closest contemporaries. This research underscores that BitEA has potential to set a new standard for register allocation through its superior speed and solution quality.
dc.description.sponsorshipScientific and Technological Research Council of Turkiye (TUBITAK) [124E044]
dc.description.sponsorshipThis work was supported by The Scientific and Technological Research Council of Turkiye (TUBITAK) 1002-B Project 124E044.
dc.identifier.doi10.1109/ACCESS.2024.3446596
dc.identifier.endpage115514
dc.identifier.issn2169-3536
dc.identifier.orcid0000-0001-6770-7674
dc.identifier.orcid0009-0006-0706-2310
dc.identifier.orcid0000-0002-2824-036X
dc.identifier.orcid0000-0001-7819-347X
dc.identifier.scopus2-s2.0-85201776670
dc.identifier.scopusqualityQ1
dc.identifier.startpage115497
dc.identifier.urihttps://doi.org/10.1109/ACCESS.2024.3446596
dc.identifier.urihttps://hdl.handle.net/20.500.14854/7343
dc.identifier.volume12
dc.identifier.wosWOS:001303408600001
dc.identifier.wosqualityQ2
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc
dc.relation.ispartofIEEE Access
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/openAccess
dc.snmzKA_WOS_20251020
dc.subjectRegisters
dc.subjectResource management
dc.subjectEvolutionary computation
dc.subjectColor
dc.subjectStatistics
dc.subjectComputer architecture
dc.subjectProgram processors
dc.subjectEvolutionary optimization
dc.subjectparallel processing
dc.subjectregister allocation
dc.subjectgraph coloring problem
dc.subjectvertex-weighted graphs
dc.subjectcrossover operator
dc.subjectevolutionary algorithms
dc.subjectk-coloring
dc.subjectBitVertex representation
dc.subjectbitwise operations
dc.titleBitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register Allocation
dc.typeArticle

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