PLODE: Precise Logic and Delay Simulator for Structural Verilog
| dc.contributor.author | Erer, Gokce Nur | |
| dc.contributor.author | Bayrakci, Alp Arslan | |
| dc.date.accessioned | 2025-10-29T12:09:47Z | |
| dc.date.issued | 2021 | |
| dc.department | Gebze Teknik Üniversitesi | |
| dc.description | 13th International Conference on Electrical and Electronics Engineering, ELECO 2021 -- Virtual, Bursa -- 176537 | |
| dc.description.abstract | Spice simulator is famous with its precision and preferred as a final stage verification tool. However, it needs a different circuit description than Verilog, and also its direct results are not meaningful in terms of speed and accuracy without further analysis. Commercial tools are proprietary and using them for conversion to Spice deck and analysis of the Spice results is costly in terms of both finance and effort. Precise Logic and Delay (PLODE) is a novel, research oriented, open source tool that can convert structural Verilog to Spice deck, perform simulations at the desired process technology node, analyze and visualize the results in terms of delay and functional accuracy. In order to help path delay based research, it can also extract a path from the circuit and simulate it without the need for a sensitizing input pair. The tool is tested and verified on ten combinational and two sequential circuits. © 2022 Elsevier B.V., All rights reserved. | |
| dc.identifier.doi | 10.23919/ELECO54474.2021.9677696 | |
| dc.identifier.endpage | 176 | |
| dc.identifier.isbn | 9786050114379 | |
| dc.identifier.scopus | 2-s2.0-85125287273 | |
| dc.identifier.scopusquality | N/A | |
| dc.identifier.startpage | 172 | |
| dc.identifier.uri | https://doi.org/10.23919/ELECO54474.2021.9677696 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.14854/14772 | |
| dc.indekslendigikaynak | Scopus | |
| dc.language.iso | en | |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | |
| dc.rights | info:eu-repo/semantics/closedAccess | |
| dc.snmz | KA_Scopus_20251020 | |
| dc.subject | Biomedical engineering | |
| dc.subject | Delay circuits | |
| dc.subject | SPICE | |
| dc.subject | 'spice' | |
| dc.subject | Circuit description | |
| dc.subject | Commercial tools | |
| dc.subject | Open source tools | |
| dc.subject | Path delay | |
| dc.subject | Process Technologies | |
| dc.subject | SPICE simulators | |
| dc.subject | Technology nodes | |
| dc.subject | Verification tools | |
| dc.subject | Computer circuits | |
| dc.title | PLODE: Precise Logic and Delay Simulator for Structural Verilog | |
| dc.type | Conference Object |








