Circuit-Level Modeling and Simulation of Read Disturbance Phenomena: RowHammer and RowPress

Abstract

As DRAM cells continue to scale down, they become increasingly susceptible to read disturbance effects such as RowHammer and RowPress. These phenomena cause bitflips in unaccessed memory regions, compromising memory isolation and data integrity in modern computing systems, with vulnerability levels increasing more than 10x over the past decade. RowHammer and RowPress have traditionally been investigated through real-world chip experiments and detailed TCAD simulations. While chip experiments demonstrate realworld vulnerability levels, they cannot reveal the underlying circuit dynamics. Meanwhile, TCAD simulations, though capable of capturing these dynamics, face significant computational limitations, restricting their analyses to small-scale cell-level studies. To address these limitations, we propose the first circuit-level SPICE-based simulation framework capable of integrating layout-induced aggressor effects and capturing key disturbance mechanisms. By aligning our framework with experimental data from off-the-shelf DDR4 modules, the proposed SPICE-based model effectively demonstrates read disturbance vulnerabilities under various operating conditions, providing a practical foundation for robust DRAM circuit design improvements. © 2025 Elsevier B.V., All rights reserved.