A High Performance Full-Word Barrett Multiplier Designed for FPGAs with DSP Resources

Abstract

Modular multiplication with large integers is the fundamental operation in public-key cryptosystems. In this paper, a high performance, full-word Barrett modular multiplier design utilizing the DSP resources in modern FPGAs is presented. The operand size of the multiplier is multiples of 528 bits. Proposed design consists of 48x48 bit multiplier blocks built from the DSP slices which perform 24x16 bit multiplications and a carry select accumulator built from the DSP slices which perform 48 bit additions. The proposed design first multiplies operands and accumulate the result and then, reduces the accumulated result using Barrett's method. A Xilinx Virtex-7 implementation of the proposed hardware takes 0.49 us and 1.88 us for 528 bit and 1056 bit modular multiplications for any modulus respectively. To the best of authors' knowledge, this is the first work which gives the detailed implementation results for full-word Barrett modular multiplier targeting FPGAs with DSP resources.