Verification of RISC-V Load and Store Instructions using a Custom Cocotb based Testbench

Abstract

The increasing complexity of modern System-on-Chip designs has introduced significant challenges in pre-silicon verification. The RISC-V Instruction Set Architecture has emerged as a pivotal framework in the modern processor design arsenal, allowing for customization of SoC implementations. This paper presents a systematic approach to simulating and testing the ISA Load/Store instructions using a custom Cocotb-based testbench. The framework developed is extensible to other ISA instructions and can be adapted for verifying different processor designs. The testing results demonstrate the core's ability to handle memory operations correctly, which is crucial for the overall performance of any processor. The success of this project demonstrates the effectiveness of using Python-based verification tools for open-source hardware projects, making them more accessible to a wider range of developers. © 2025 Elsevier B.V., All rights reserved.