Verification of RISC-V R-type Instructions Using A Custom Cocotb Based Approach

Abstract

Verifying System-on-Chip designs has become increasingly challenging due to the growing complexity and stringent requirements of modern architectures. The RISC-V instruction set architecture provides a flexible and efficient framework for integrating IP cores with the processor, enabling seamless customization of SoC designs. In this work, we present a systematic and scalable Cocotb-based verification approach for commonly used RISC-V R-type instructions, including ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLR, and SLT. The proposed methodology can be extended to verify the full RISC-V ISA, making it adaptable for comprehensive core verification. Our test study on the PicoRV32, a RISC-V core with RV32I ISA, demonstrates that R-type instructions can be verified with high coverage rates exceeding 89%. This study highlights the potential of Cocotb, a free and open-source Python-based verification framework, in making hardware verification tools more accessible to designers with limited budgets. © 2025 Elsevier B.V., All rights reserved.