Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis

Abstract

Several automatic analog integrated circuit (IC) sizing tools have been proposed and successfully applied to multi-objective circuit design problems over the last two decades. However, rendering those tools yield aware has not been fully addressed yet since inclusion of variability analysis to the optimization loop is still a bottleneck due to the tremendous trade-off between accuracy and efficiency of the synthesis process. Conventional Monte Carlo (MC) based approaches are quite accurate, but, they are highly inefficient due to cumbersome simulation effort. Even though employing enhanced sampling techniques, e.g., Latin Hypercube Sampling (LHS), exhibits slightly better efficiency, the accuracy of such approaches is still less than Monte Carlo. To palliate this problem, in this paper, we propose a novel Deep Neural Network (DNN) aided MC simulation framework for yield-aware analog circuit sizing. In the developed tool, the DNN is leveraged to develop circuit models during the optimization, which are then used to estimate the effects of variations in device dimensions without any simulation effort while some additional simulations are concurrently carried out for Vth variations. Finally, once DNN based circuit models are obtained, the simulator is replaced by those models during the MC analysis, which enables performing expanded MC for accurate yield estimations without running any simulations. To demonstrate the developed tool, three analog circuits were optimized, a single stage-active loaded amplifier, a two stage amplifier, and a voltage comparator. According to the synthesis results, the proposed approach can achieve up to 96.61% reduction in overall execution time (29x speed-up).