Stochastic logical effort as a variation aware delay model to estimate timing yield

Abstract

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180 x on the average for ISCAS'85 benchmark circuits and in the existence of both inter- and intra-die variations. (C) 2014 Elsevier B.V. All rights reserved.