Step size determination approach for aging simulations in analog ICs

Abstract

Simulation of time-dependent variations is quite complicated since the degradation is a function of time, where the time step directly affects the accuracy and the efficiency of the analysis. Commercial tools use a constant step count during simulations, in which choosing a large step count may degrade the efficiency whereas keeping it small may result in accuracy problems. To overcome this problem, a couple of different adaptive time-step approaches have been proposed in the literature. Nevertheless, they suffer from the initial workload during step count determination or some other accuracy problems. In this study, we present a two-level step count determination approach. At the first level, the step count induced estimation error can be promptly determined via an effective simulation strategy. At the second level, the error is fitted into a saturated power law model; thus, the efficient step count can be determined without any simulation effort. The proposed approach provides a remarkable save in computation time and can be used for all analog circuits without loss of generality. © 2021 Elsevier B.V., All rights reserved.